1. Field of the Invention
The present invention relates to an information processing technique, and more particularly to an information processing technique for realizing high performance with parallel instruction processing by adopting pipeline processing, out-of-order processing, etc.
2. Description of the Related Art
If there is an interference relationship of an instruction operand, that is, if there is a relationship where the contents of a resource updated by a preceding instruction are referenced by a succeeding instruction within an information processing device, the state where the preceding instruction affects the execution of the succeeding instruction, for example, the state where the succeeding instruction cannot be executed until the execution of the preceding instruction is completed, occurs. If it is necessary to guarantee the same result as that in the case where instructions are sequentially executed in the order instructed by an instruction program, the instructions cannot be executed in parallel. Therefore, the hardware performance for realizing a high throughput cannot be fully utilized, which leads to a degradation of the overall performance of the information processing device.
Among such operand interference relationships, the register interference state where the contents of a register updated by a preceding instruction are used and referenced by a succeeding instruction, by way of example, for the generation of a main storage operand address, is an EGI (Execute Generate Interlock). The EGI is a principal factor that degrades the entire throughput of an information processing device.
Such register interference occurs due to the time difference between when the contents of a register are normally updated by a preceding instruction upon completion of instruction processing, and when an operand address is generated by a succeeding instruction in a relatively early stage of the instruction processing.
As a means for reducing the occurrences of the register interference, the method for directly bypassing data yet to be stored in a register to an adder for generating an operand address, that is, an EAG (Effective Address Generator) is implemented. FIG. 1 shows the pipeline processing performed in such a case.
The upper portion of FIG. 1 shows the operations of instruction pipeline processing in the case where no register interference state, that is, no EGI occurs. These pipeline operations are composed of a cycle D for decoding an instruction, a cycle A for generating an address, a cycle T for translating an address by using accesses to a translation look-aside buffer and a tag, a cycle B for reading an operand from a buffer, a cycle U, for example, for executing an arithmetic operation and updating an RUB (Register Update Buffer), and a cycle W for writing a result of the arithmetic operation to a GR (General-purpose Register). The operand for the arithmetic operation is loaded from an LBS (Local Buffer Storage) to an LR (Load data Register) on the cycle B, and is used for executing the arithmetic operation on the cycle U.
The lower portion of FIG. 1 explains the pipeline operations when register interference occurs. The EGI as the register interference state is detected by an EGI detecting circuit not shown in this figure according to the result of instruction decoding. An address calculation is postponed until the contents of a BR (Base Register), an XR (index Register), and a DR (Displacement Register), which are required for calculating an address of a main storage operand, are established on the cycle A. Then, the data to be stored in the BR and the XR are provided from the LBS as EA1 and EA2 by bypassing the BR and the XR, and the value of the DR is provided as EA3 on a priority cycle Pa of the address calculation, so that the operand address is generated by an EAG on the address generation cycle A. Here, an arithmetic operation execution cycle X precedes the update cycle U and is independent therefrom, and the result of the arithmetic operation is once stored in an RR (Result Register).
As explained by referring to FIG. 1, even an information processing device equipped with high performance cache has a problem in that a plurality of cycles are lost and the parallel processing capability of instruction execution significantly degrades, because the establishment of the contents of a register to be updated by a preceding instruction must be waited for, even if the contents of the register, which are used for an address calculation, are bypassed and used before being stored in the register. The more superior the parallel processing capability the information processing device possesses for the realization of high performance, the greater the number of cycles are lost. As a result, specifically designed high performance cannot be fully utilized.
The present invention aims at overcoming the above described problems, and at providing an information processing device and method for preventing performance from being degraded by storing an operand address generated by a succeeding instruction as a previous execution result when an EGI occurs, by estimating an operand address based on the previous execution result, and by starting instruction execution before generating an actual operand address.
The information processing device according to the present invention includes a detector which detects a register interference state where a register whose contents are rewritten by a preceding instruction is used by a succeeding instruction so as to generate an operand address, and an operand address history storage which stores the operand address generated when a succeeding instruction is executed in association with the address of the succeeding instruction, if the register interference state is detected by the detector.
The operand address history storage may include an area for storing a branch destination address obtained when a branch instruction is executed in association with the address of the branch instruction, and a flag for making a distinction from the area where the operand address is stored in association with the address of the succeeding instruction.
Additionally, the information processing device according to the present invention may further include an instruction fetcher which presents an operand address along with an fetched instruction to an instruction executing unit for executing the fetched instruction, when the operand address is retrieved from the contents stored within the operand address history storage by using the address of the fetched instruction at the time of the instruction fetch operation from main storage.
Furthermore, the information processing device according to the present invention may further include a reservation station which stores the operand address presented by the instruction fetcher along with the address of the fetched instruction in order to perform a stack process for holding instructions to be executed.
Still further, the instruction executing unit included in the information processing device according to the present invention may start instruction execution including the fetch operation of a main storage operand by using the presented operand as an estimated operand address prior to the generation of the operand address corresponding to the fetched instruction, when the operand address retrieved from the operand address history storage is presented by the instruction fetcher.
Still further, the information processing device according to the present invention may further include an operand address comparator which stores an estimated operand address when instruction execution is started by using the presented operand address as the estimated operand address, and for making a comparison between the estimated operand address and the operand address generated when the register used by the fetched instruction in order to generate an operand address becomes available, wherein if these two operand addresses match, the execution of the process corresponding to the fetched instruction is continued unchanged.
Still further, the instruction executing unit included in the information processing device according to the present invention may further invalid the result of the instruction execution with the estimated operand address, and for re-executing the instruction by using the generated operand address, if the operand address comparator detects that the two operand addresses mismatch.
Still further, the operand address history storage may further store as control information the information about an event which causes an estimated operand address error in association with the address of the succeeding instruction, if the operand address comparator detects that the two operand addresses mismatch.
Still further, the operand address history storage may further store the estimated operand address error in association with the address of the succeeding instruction, and at the same time, the instruction executing unit included in the information processing device according to the present invention may further postpone the execution of a succeedingly fetched instruction until an operand address is generated after the register used by the succeedingly fetched instruction in order to generate an operand address becomes available, even if the estimated operand address is retrieved from the contents stored within the operand address history storage according to the address of the succeedingly fetched instruction at the time of the fetch operation of the instruction succeeding the fetched instruction from the main storage, if the operand address comparator detects that the two operand addresses mismatch.
Still further, the information processing device according to the present invention may further include a second instruction fetcher which modifies a stored estimated address based on the control information, and for presenting to the instruction executing unit which executes the fetched instruction the modified address as a newly estimated address along with the succeedingly fetched instruction, when the control information is retrieved from the contents stored within the operand address history storage according to the address of the succeedingly fetched instruction at the time of the fetch operation of the instruction succeeding the fetched instruction from the main storage.
An information processing method according to the present invention includes: a first step of detecting a register interference state where a register whose contents are rewritten by a preceding instruction is used by a succeeding instruction so as to generate an operand address; and a second step of storing the operand address generated when the succeeding instruction is executed, in association with the address of the succeeding instruction when the register interference state is detected in the first step.
Additionally, the information processing method according to the present invention may further include a third step of presenting the operand address along with a fetched instruction to an instruction executing unit which executes the fetched instruction, when the operand address is retrieved from the contents stored in the second step according to the address of the fetched instruction at the time of the fetch operation of the instruction from the main storage.
Furthermore, the third step may include a step of making the instruction executing unit start the instruction execution including the fetch operation of a main storage operand by using the presented operand address as an estimated operand address prior to the generation of the operand address corresponding to the fetched instruction, when the operand address retrieved from the contents stored in the second step is presented.
Still further, the information processing method according to the present invention may further include a fourth step of storing an estimated operand address, and of making a comparison between the estimated operand address and the operand address generated when the register used by the fetched instruction in order to generate an operand address becomes available, when the presented operand address is used as the estimated operand address, wherein the execution of the process corresponding to the fetched instruction is continued unchanged if the two operand addresses match.
Still further, the information processing method according to the present invention may further include a step of invalidating the result of the instruction execution by using the estimated operand address, and of re-executing the instruction by using the generated operand address, if a mismatch between the two operand addresses is detected in step four.
The above described information processing device and method can be respectively implemented by using computers. To make a computer implement an information processing algorithm, the above described method is represented as a computer program.
A (storage) medium according to the present invention is a computer-readable medium storing a program which enables a computer to implement information processing. Its execution method corresponds to the above described method according to the present invention. This medium can be implemented as an external storage medium such as an optical storage medium including a CD-ROM, etc., a magnetic storage medium including a floppy disk, etc., or an internal storage medium including a hard disk, a ROM, a RAM, etc.
As described above, according to the present invention, it becomes possible to start the execution of a succeeding instruction by using an estimated operand address as a previous execution result before an actual operand address is generated.